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LOCATION:505
DTSTART;TZID=America/Denver:20231112T111900
DTEND;TZID=America/Denver:20231112T113500
UID:submissions.supercomputing.org_SC23_sess421_ws_rsdha108@linklings.com
SUMMARY:Accelerator Integration in a Tile-Based SoC:  Lessons Learned with
  a Hardware Floating Point Compression Engine
DESCRIPTION:Workshop\n\nXueyang Liu (Georgia Institute of Technology); Pat
 ricia Gonzalez-Guerrero (Lawrence Berkeley National Laboratory (LBNL)); Iv
 y (Bo) Peng (KTH Royal Institute of Technology, Sweden); Ronald Minnich (S
 amsung Corporation); and Maya Gokhale (Lawrence Livermore National Laborat
 ory (LLNL))\n\nHeterogeneous Intellectual Property (IP) hardware accelerat
 ion engines have emerged as a viable path forward to improving performance
  in the waning of Moore’s Law and Dennard scaling. In this study, we desig
 n, prototype, and evaluate the HPC-specialized ZHW floating point compress
 ion accelerator as a resource on a System on Chip (SoC). Our full hardware
 /software implementation and evaluation reveal inefficiencies at the syste
 m level that significantly throttle the potential speedup of the ZHW accel
 erator. By optimizing data movement between CPU, memory, and accelerator, 
 6.9X is possible compared to a RISC-V64 core, and 2.9X over a Mac M1 ARM c
 ore.\n\nTag: Accelerators, Edge Computing, Heterogeneous Computing\n\nRegi
 stration Category: Workshop Reg Pass\n\nSession Chairs: Ali Akoglu (Univer
 sity of Arizona), Mehmet E Belviranli (Colorado School of Mines), and Seyo
 ng Lee (Oak Ridge National Laboratory (ORNL))
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