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DTSTART;TZID=America/Denver:20231113T121000
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UID:submissions.supercomputing.org_SC23_sess447_ws_pmbss112@linklings.com
SUMMARY:Hardware Specialization:  Estimating Monte Carlo Cross-Section Loo
 kup Kernel Performance and Area
DESCRIPTION:Kazutomo Yoshii, John Tramm, and Bryce Allen (Argonne National
  Laboratory (ANL)); Tomohiro Ueno and Kentaro Sano (RIKEN Center for Compu
 tational Science (R-CCS)); and Andrew Siegel and Pete Beckman (Argonne Nat
 ional Laboratory (ANL))\n\nHardware specialization is one of the promising
  directions in the post-Moore era.  It is imperative to understand how har
 dware specialization paradigms can benefit HPC.  An essential question rev
 olves around estimating the theoretical performance of an optimally specia
 lized architecture without requiring extensive hardware development expert
 ise and efforts.\n\nFocusing on the Monte Carlo cross-section lookup kerne
 l, known for its notably low resource utilization, we develop a workflow t
 o simulate a specialized architecture's timing and estimate resource usage
  to answer these questions, leveraging open-source hardware tools. We impl
 ement building blocks of the kernel pipeline in the Chisel construction la
 nguage and generate Verilog codes for resource estimation. Our late-breaki
 ng results show that the kernel latency is 46 cycles per lookup while the 
 optimized CPU code takes 680 cycles, and a potential 15k pipeline copies w
 ithin a 698 mm2 die, reflective of the Intel Xeon Platinum 8180 dimensions
 .\n\nTag: Modeling and Simulation, Performance Measurement, Modeling, and 
 Tools\n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Simon
  Hammond (National Nuclear Security Administration (NNSA)); Stephen Jarvis
  (University of Birmingham, UK); and Steven A. Wright (University of York,
  England)\n\n
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