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UID:submissions.supercomputing.org_SC23_sess451_misc234@linklings.com
SUMMARY:Performance Portability in the Age of Extreme Heterogeneity
DESCRIPTION:Workshop\n\nJohn Shalf (Lawrence Berkeley National Laboratory 
 (LBNL))\n\nMoore’s Law is a techno-economic model that has enabled the IT 
 industry to double the performance and functionality of digital electronic
 s roughly every 2 years within a fixed cost, power and area. This expectat
 ion has led to a relatively stable ecosystem (e.g. electronic design autom
 ation tools, compilers, simulators and emulators) built around general-pur
 pose processor technologies, such as the x86, ARM and Power instruction se
 t architectures. However, the historical improvements in performance offer
 ed by successive generations of lithography are waning while costs for new
  chip generations are growing rapidly. In the near term, the most practica
 l path to continued performance growth will be architectural specializatio
 n in the form of many different kinds of accelerators. New software implem
 entations, and in many cases new mathematical models and algorithmic appro
 aches, are necessary to advance the science that can be done with these sp
 ecialized architecture. This trend will not only continue but also intensi
 fy as the transition from multi-core systems to hybrid systems has already
  caused many teams to re-factor and redesign their implementations. But th
 e next step to systems that exploit not just one type of accelerator but a
  full range of heterogeneous architectures will require more fundamental a
 nd disruptive changes in algorithm and software approaches. This applies t
 o the broad range of algorithms used in simulation, data analysis and lear
 ning. New programming models or low-level software constructs that hide th
 e details of the architecture from the implementation can make future prog
 ramming less time-consuming, but they will not eliminate nor in many cases
  even mitigate the need to redesign algorithms. Future software developmen
 t will not be tractable if a completely different code base is required fo
 r each different variant of a specialized system.\n\nThe aspirational desi
 re for “minimizing the number of lines of code that must be changed to mig
 rate to different systems with different arrangements of specialization” i
 s encapsulated in the loaded phrase “Performance Portability.” However, pe
 rformance portability is likely not an achievable goal if we attempt to do
  it using imperative languages like Fortran and C/C++. There is simply not
  enough flexibility built in to the specification of the algorithm for a c
 ompiler to do anything other than what the algorithm designer explicitly s
 tated in their code. To make this future of diverse accelerators usable an
 d accessible in the former case will require the co-design of new compiler
  technology and domain- specific languages (DSLs) designed around the requ
 irements of the target computational motifs. The higher levels of abstract
 ion and declarative semantics offered by DSLs enable more degrees of freed
 om to optimally map the algorithms onto diverse hardware than traditional 
 imperative languages that over-prescribe the solution. Because this will d
 rastically increase the complexity of the mapping problem, new mathematics
  for optimization will be developed, along with better performance introsp
 ection (both hardware and software mechanisms for online performance intro
 spection) through extensions to the roofline model. Use of ML/AI technolog
 ies will be essential to enable analysis and automation of dynamic optimiz
 ations.\n\nTag: Large Scale Systems, Middleware and System Software, Progr
 amming Frameworks and System Software\n\nRegistration Category: Workshop R
 eg Pass\n\nSession Chairs: Dhabaleswar K. (DK) Panda (Ohio State Universit
 y), Karl Schulz (Advanced Micro Devices (AMD) Inc), Aamir Shafi (Ohio Stat
 e University), and Hari Subramoni (Ohio State University)
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