Contributor

I'm a Postdoctoral Researcher in the Department of Computer Science and Engineering, School of Electronic Information and Electrical Engineering (SEIEE) at Shanghai Jiao Tong University (SJTU). Now, I'm working in the Sustainable Architectures and Infrastructure Laboratory ( SAIL) as a part of the Emerging Parallel Computing Center (EPCC). My advisors are Professor Chao Li and Professor Minyi Guo, and now my co-advisor is Professor Xiaokang Yang. I received my PH.D. degree from SJTU in Mar 2024. My primary research area is memory system and architecture design for emerging applications. Recently, I'm interested in disaggregated memory, resource scheduling, heterogeneous architecture, graph processing, AIGC, etc.