Session <Full Schedule · Contributors · Organizations · Search Program · My Schedule · Happening Now · MapsMore…Search ProgramMy ScheduleHappening NowMapsWorkshop: Second International Workshop on RISC-V for HPCSession ChairsJohn LeidelTactical Computing Laboratories LLCTexas Tech UniversityNick BrownEdinburgh Parallel Computing Centre (EPCC)University of EdinburghMichael WongCodeplay Software Ltd, UKKhronos Group IncJohn DavisOpenchipAndy GothardSiemensEvent TypeWorkshopTimeMonday, 13 November 20232pm - 5:30pm MSTLocation507Tags Architecture and Networks Hardware Technologies Registration Categories W Presentations2:00pm - 2:05pm MSTIntroduction and WelcomePresenterNick Brown2:05pm - 2:40pm MSTRISC-V EverywherePresenterMark Himelstein2:40pm - 2:45pm MSTLightning Vendor Talk: Esperanto Technologies ET-SoC for AI and ML WorkloadsPresenterLee Flanagin2:45pm - 2:50pm MSTLightning Vendor Talk: The InspireSemi Next Gen Thunderbird Compute Accelerator for HPC, AI, and Graph AnalyticsPresenterDoug Norton2:50pm - 2:55pm MSTLightning Vendor Talk: SG2042 Empowering RISC-V in High-Performance ComputingPresenterLiuxi Yang2:55pm - 3:00pm MSTLightning Vendor Talk: E4 Experience with RISC-V in HPCPresenterDaniele Gregori3:00pm - 3:30pm MSTRISC-V for HPC – Afternoon Break3:30pm - 3:50pm MSTAn Empirical Comparison of the RISC-V and AArch64 Instruction SetsAuthor/PresentersDaniel WeaverSimon McIntosh-Smith3:50pm - 4:10pm MSTEvaluating HPX and Kokkos on RISC-V Using an Astrophysics Application Octo-TigerAuthor/PresentersPatrick DiehlGregor DaissSteven BrandtAlireza KheirkhahanHartmut KaiserChristopher TaylorJohn Leidel4:10pm - 4:30pm MSTIs RISC-V Ready for HPC Prime-Time: Evaluating the 64-Core Sophon SG2042 RISC-V CPUAuthor/PresentersNick BrownMaurice JamiesonJoseph Lee4:30pm - 4:50pm MSTShort Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-VAuthor/PresentersPablo VizcainoGeorgios LeronymakisNikolaos DimouVassilis PapaefstathiouJesus LabartaFilippo Mantovani4:50pm - 5:10pm MSTAutomatic Generation of Micro-Kernels for Performance Portability of Matrix Multiplication on RISC-V Vector ProcessorsAuthor/PresentersFrancisco IgualLuis PiñuelSandra CatalánHéctor MartínezAdrián CastellóEnrique Quintana-Ortí5:10pm - 5:30pm MSTChallenges and Opportunities in the Co-Design of Convolutions and RISC-V Vector ProcessorsAuthor/PresentersSonia Rani GuptaNikela PapadopoulouMiquel Pericàs5:30pm - 6:00pm MSTSecond International Workshop on RISC-V for HPCOrganizersNick BrownJohn DavisJohn LeidelMichael WongAndy Gothard